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Microchip Technology /ATSAML11E14A /PM /STDBYCFG

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Interpret as STDBYCFG

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DEFAULT)PDCFG 0 (0)DPGPDSW 0 (AUTO)VREGSMOD 0 (BBIASHS)BBIASHS 0 (BBIASTR)BBIASTR

PDCFG=DEFAULT, VREGSMOD=AUTO, DPGPDSW=0

Description

Standby Configuration

Fields

PDCFG

Power Domain Configuration

0 (DEFAULT): PDSW power domain switching is handled by hardware.

1 (PDSW): PDSW is forced ACTIVE.
DPGPDSW

Dynamic Power Gating for PDSW

0 (0): Dynamic Power Gating disabled

1 (1): Dynamic Power Gating enabled
VREGSMOD

Voltage Regulator Standby mode

0 (AUTO): Automatic mode

1 (PERFORMANCE): Performance oriented

2 (LP): Low Power oriented
BBIASHS

Back Bias for HSRAM
BBIASTR

Back Bias for Trust RAM

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data